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Integrated Circuit Systems, Inc.
ICS9248-65
Frequency Timing Generator for PENTIUM IISystems
Features
Generates the following system clocks: - 3 CPU clocks ( 2.5V, 100/133MHz) - 10 PCI clocks, including 1 free-running (3.3V, 33.3MHz) - 1 CPU/2 clocks (2.5V, 50/66.6MHz) - 1 IOAPIC clocks (2.5V, 16.67MHz) - 3 Fixed frequency 66MHz clocks(3.3V, 66.6MHz) - 2 REF clocks(3.3V, 14.318MHz) - 1 USB clock (3.3V, 48MHz) Efficient power management through PD#. 0 to -0.5% typical down spread modulation on CPU, PCI, IOAPIC, 3V66 and CPU/2 output clocks. Uses external 14.318MHz crystal.
Key Specification
CPU Output Jitter: <250ps CPU/2 Output Jitter. <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps PCI Output Jitter. <500ps Ref Output Jitter. <1000ps CPU 0:2 Output Skew: <175ps PCI_F, PCI 1:7 Output Skew: <500ps 3V66_0:2 Output Skew <250ps CPU to 3V66_0:2 Output Offset: 0.0 - 1.5ns (CPU leads) 3V66 to PCI Output Offset: 1.5 - 4ns (CPU leads) CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)

Block Diagram
Pin Configuration
48-pin SSOP
Third party brands and names are the property of their respective owners. 9248-65 Rev C 7/28/99
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-65
General Description
The ICS9248-65 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9211-01. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-65 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG.
Power Groups:
VDDREF, GNDREF = REF, X1, X2 GNDPCI, VDDPCI = PCICLK VDD66, GND66 = 3V66 VDD48, GND48 = 48MHz VDDCOR, GNDCOR = PLL Core VDDLCPU/2 , GNDLCPU/2 = CPU/2 VDDLIOAPIC, GNDIOAPIC = IOAPIC
Pin Descriptions
Pin number Pin name
1,2 REF 3, 9, 17, 24, VDD 28, 34 4 X1 5 X2 6,14, 20, 26, GND 33, 45, 48 7 PCICLK_F 8,10,11,12,13, PCICLK (1:9) 15,16,18,19 21,22,23 3V66 25 SEL 133/100# 48 MHz SEL (0:1) SPREAD# PD# GNDLCPU CPUCLK (0:2) VDDLCPU GNDLCPU/2 CPU/2 VDDLCPU/2 IOAPIC(0:1) VDDIOAPIC
Type
Output Power Input Output Power Output Output Output Input 3.3 V power for clock outputs. 14.318 MHz crystal input 14.318 MHz crystal output Ground for clock outputs
Description
3.3V, 14.318 MHz reference clock output.
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP# 3.3 V PCI clock outputs, generating timing requirements for 3.3 V 66 MHz clock output, fixed frequency clock typically used with AGP Control for the frequency of clocks at the CPU output pins. If logic "0" is used the 100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases. 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices Frequency select pin , logic input. Power-on spread spectrum enable option. Active low = spread spectrum clocking enable. Active high = spread spectrum clocking disable. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. Ground for the CPU and Host clock outputs 2.5 V CPU and Host clock outputs 2.5 V power for the CPU and Host clock outputs Ground for the CPU and Host clock outputs Output running at 1/2 CPU clock frequency.Synchronous to the CPU outputs. 2.5 V power for the CPU/2 clock outputs 2.5V fixed 16.6 MHz IOAPIC clock outputs 2.5V power for IOAPIC clock
27 29,30 31 32 35,39 36,37,40 38,41 42 43 44 46 47
Output Input Output Input Power 0utput Power Power Output Power Output Power
2
ICS9248-65
Frequency Select:
SEL SEL1 SEL0 133/100# 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 CPU MHz Hi-Z N/A 100 CPU/2 MHz Hi-Z N/A 50 3V66 MHz Hi-Z N/A 66.6 PCI MHz Hi-Z N/A 33.3 48 MHz Hi-Z N/A Hi-Z REF MHz Hi-Z N/A 14.318 IOAPIC MHz Hi-Z N/A 16.67 Comments Tri-state Reserved 48MHz PLL disabled Test mode (1) Reserved
10 0 50 TCLK/2 TCLK/4 N/A N/A 133.3 66 133.3 66
66.6 33.3 48 TCLK/4 TCLK/8 TCLK/2 N/A N/A N/A 66 33 Hi-Z 66 33 48
14.318 16.67 TCLK TCLK/16 N/A N/A 14.318 16.67 14.318 16.67
Note: 1. TCLK is a test clock driven on the x1 input during test mode.
ICS9248-65 Power Management Features:
PD# 0 1 CPUCLK CPU/2 IOAPIC LOW ON LOW ON LOW ON 3V66 LOW ON PCI LOW ON PCI_F LOW ON REF. 48MHz LOW ON Osc OFF ON VCOs OFF ON
Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Late ncy Singal Singal State 1 (normal operation) 0 (power down) No. of ris ing e dge s of PCICLK 3mS 2max.
PD#
Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
3
ICS9248-65
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
4
ICS9248-65
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Offset
Group CPU to 3V66 3V66 to PCI CPU to IOAPIC Offset 0.0-1.5ns CPU leads 1.5-4.0ns 3V66 leads 1.5-4.0ns CPU leads Measurement Loads CPU @ 20pF, 3V66 @ 30pF 3V66 @ 30pF, PCI @ 30pF CPU @ 20pF, IOAPIC @ 20pF Measure Points CPU @1.25V, 3V66 @ 1.5V 3V66 @ 1.5V, PCI @ 1.5V CPU @1.25V, IOAPIC @ 1.5V
No te: 1 . All o ffsets are to be meas u red at ris in g edg es.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = VDDL = 3.3 V +/-5%, (unless otherwise stated)
PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP100 IDD3.3OP133 IDD3.3OP144 IDD3.3OP154 IDD3.3PD Fi CIN CINX Ttrans Ts TSTAB CONDITIONS MIN 2 VSS-0.3 -5 -200 TYP MAX UNITS VDD+0.3 V 0.8 V A 5 A A
Operating
Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time
1
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133.3 MHz CL = 0 pF; Select @ 144 MHz CL = 0 pF; Select @ 154 MHz CL = 0 pF; PWRDWN# = 0 VDD = 3.3 V Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq.
0.1 2.0 -100 65 71 75 78 64 14.318 36 1 0.5
160
mA
200 16 5 45 3 3
A
MHz pF pF ms ms ms
12 27
Clk Stabilization 1
Skew Skew Skew
1
1 1 1
tCPU-PCI tCPU-3V66 t3V66-PCI
VT = 1.5 V; VTL = 1.25 V VT = 1.5 V; VTL = 1.25 V VT = 1.5 V
1.5
2.4 1.4 1.4
4 1.5 4
ns ns ns
Guaranteed by design, not 100% tested in production.
5
ICS9248-65
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current Skew
1 1 1
SYMBOL IDD2.5OP100 IDD2.5OP133 IDD2.5OP144 IDD2.5OP154 IDD2.5PD tCPU-PCI tCPU-3V66 tCPU-IOAPIC
CONDITIONS CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133.3 MHz CL = 0 pF; Select @ 144 MHz CL = 0 pF; Select @ 154 MHz CL = 0 pF; PWRDWN# = 0 VT = 1.5 V; VTL = 1.25 V VT = 1.5 V; VTL = 1.25 V VTL = 1.25 V
MIN
TYP 14 18 19 20 0.3 2.4 1.4 1.4
MAX UNITS 30 mA 30 30 30 A 100 4 1.5 4 ns ns ns
1.5
Skew Skew
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute Jitter, Cycle-to-cycle
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B tf2B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, Freq. < 124 MHz VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
TYP 2.3 0.31 -39 27 0.95 1
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 55 175 150 +250 250 ns ns % ps ps ps ps
d t2B1 tsk2B1 tj12B1 tjabs2B1 tjcyc-cyc2B1
45
50 22 21
-250
55 110
Guaranteed by design, not 100% tested in production.
6
ICS9248-65
Electrical Characteristics - CPU/2
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute Jitter, Cycle-to-cycle
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B
1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, Freq. < 124 MHz VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
TYP 2.3 0.31 -33 27 1.1 1
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 55 150 +250 250 ns ns % ps ps ps
tf2B1 d t2B1 tj12B1 tjabs2B1 tjcyc-cyc2B1
45 -250
48 13 42 100
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1 1 tjabs1 tjcyc-cyc1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
25 0.5 0.5 45
TYP 3.1 0.17 -61 45 1.8 1.7 51 37 16
MAX UNITS V 0.4 V -22 mA mA 2 2 55 500 150 250 500 ns ns % ps ps ps ps
Duty Cycle
Jitter, One Sigma
Jitter, Absolute Jitter, Cycle-to-cycle1
1
1
-250
50 130
Guaranteed by design, not 100% tested in production.
7
ICS9248-65
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1 1 tjabs1 tjcyc-cyc1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
25
TYP 3.1 0.17 -62 45 1.5 1.6
MAX UNITS V 0.4 V -22 mA mA 2 2 55 500 150 250 500 ns ns % ps ps ps ps
Duty Cycle
45
50 310 11
Jitter, One Sigma
Jitter, Absolute Jitter, Cycle-to-cycle1
1
1
-250
45 105
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B Tj1 4B Tjabs4B
tjcyc-cyc4B
CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
TYP 2.4 0.17 -61 53 0.75 0.675
MAX UNITS V 0.4 V -19 mA mA 2.2 2 55 150 500
500
ns ns % ps ps
ps
Duty Cycle
45 -500
49.5 26 137
200
Jitter, One Sigma
Jitter, Absolute Jitter, Cycle-to-cycle1
1
1
Guaranteed by design, not 100% tested in production.
8
ICS9248-65
Electrical Characteristics - REF, 48MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1 5 tjabs5 tj1 5 tjabs5
CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, REF VT = 1.5 V, REF VT = 1.5 V, 48 MHz VT = 1.5 V, 48 MHz
MIN 2.4
16
TYP 2.9 0.33 -31 23 1.8 2.1
MAX UNITS V 0.4 V -22 mA mA 4 4 55 150 500 150 250 ns ns % ps ps ps ps
Duty Cycle
45 -500 -250
52 85 285 32 110
Jitter, One Sigma Jitter, Absolute Jitter, Absolute
1
1 1
Jitter, One Sigma
1
Guaranteed by design, not 100% tested in production.
9
ICS9248-65
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
48 Pin SSOP Package
Ordering Information
Example:
ICS9248yF-65
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
10
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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